BIDIR_L=UP, BIDIR_H=UP
SCT control register
| DOWN_L | This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. |
| STOP_L | When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events related to the counter can occur. If a designated start event occurs, this bit is cleared and counting resumes. |
| HALT_L | When this bit is 1, the L or unified counter does not run and no events can occur. A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, only software can clear this bit to restore counter operation. This bit is set on reset. |
| CLRCTR_L | Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. |
| BIDIR_L | L or unified counter direction select 0 (UP): Up. The counter counts up to a limit condition, then is cleared to zero. 1 (UP_DOWN): Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. |
| PRE_L | Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. |
| DOWN_H | This bit is 1 when the H counter is counting down. Hardware sets this bit when the counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit when the counter is counting down and a limit condition occurs or when the counter reaches 0. |
| STOP_H | When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to the counter can occur. If such an event matches the mask in the Start register, this bit is cleared and counting resumes. |
| HALT_H | When this bit is 1, the H counter does not run and no events can occur. A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the halt condition while keeping the SCT in the stop condition (not running) with a single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit can only be cleared by software to restore counter operation. This bit is set on reset. |
| CLRCTR_H | Writing a 1 to this bit clears the H counter. This bit always reads as 0. |
| BIDIR_H | Direction select 0 (UP): The H counter counts up to its limit condition, then is cleared to zero. 1 (UP_DOWN): The H counter counts up to its limit, then counts down to a limit condition or to 0. |
| PRE_H | Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. |